Voltage boosting circuit for an integrated circuit device

ABSTRACT

A voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit. The booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal. The voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit. The voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage. The pulse generator generates a pulse signal responsive to the detected voltage signal. And the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.

[0001] This application claims the priority benefit of Korean PatentApplication No. 2000-69982, filed on Nov. 23, 2000, the contents ofwhich are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to the field of an integratedcircuit device, and more particularly to a voltage boosting circuit foran integrated circuit device.

BACKGROUND OF THE INVENTION

[0003] Nonvolatile semiconductor memory devices for integrated circuitdevices are expected to experience a sharp increase in market demand.That is because such devices (and especially flash memory devices) willbe used in portable devices such as cellular phones and personal digitalassistants (PDAs).

[0004] Portable devices are limited by their batteries. To reduce powerconsumption, portable devices strive to operate on lower power supplyvoltages. This extends their usage time from a single battery, andresults in these devices becoming lighter.

[0005] While the available power supply voltages are becoming lower, theintegrated circuit devices compensate for this by generating highervoltages internally. This is accomplished by boosting circuits, whichuse a boosting mechanism to generate a high voltage (hereinafter referto as boosted voltage).

[0006] One of the challenges is to maintain the boosted voltage uniform,even though the level of the external power supply voltage changes. Ifthe boosted voltage is instead permitted to fluctuate, the appliedvoltage to MOS transistors also fluctuates. This causes serious problemsin operating the integrated circuit device. For example, there may be amalfunction by applying an excessive high voltage. That is because avoltage higher than a breakdown voltage is applied to a p-n junction inthe integrated circuit device. Further, there may also be a destructionof an insulation film in the MOS transistors, which would suddenlyincrease power consumption.

[0007] Referring now to FIG. 1, a method has been developed to reducethe fluctuation of a boosted voltage, when a power supply voltage isvaried. The method is proposed in the paper titled “A 2.7V Only 8 Mb'16NOR Flash Memory” (IEEE 1996 Symposium On VLSI Circuits Digest ofTechnical Papers, pp. 172-173). The voltage boosting circuit of theproposed paper is reproduced in FIG. 1.

[0008] Referring to FIG. 1, the essence of the method is to control thenumber of capacitors used in the boosting mechanism. A conventionalvoltage boosting circuit is constructed of a booster 10 and a controllogic 12. The booster 10 includes two inverters 20 and 24, twocapacitors 22 and 26, and a PMOS transistor 28, connected as shown inFIG. 1.

[0009] The booster 10 generates a boosted voltage VPP higher than apower supply voltage VCC, in response to a low-to-high transition of acontrol signal. According to a control signal Vcdet, the control logic12 determines the number of capacitors to be used in the booster 10 byan alternative selection of inverters 20 and 24 in the booster 10. Avoltage level of the control signal Vcdet can be determined by a voltagedivider (not shown), for dividing the boosted voltage VPP.

[0010] If the voltage level of the control signal Vcdet rises inaccordance with an increase of the boosted voltage VPP, the controllogic 12 disables one of inverters 20 and 24 used in the booster 10.Namely, the booster 10 operates by using one capacitor, and thereforethe VPP is decreased by about a half. If the VPP becomes low, thecontrol logic 12 enables a disabled inverter. The booster 10 thenoperates by using the two capacitors 22, 26, and therefore the VPPbecomes high again.

[0011]FIG. 2 is a graph showing a relation of fluctuation of the powersupply voltage and variation of boosted voltage in a conventionalvoltage boosting circuit. If the power supply voltage is positionedbetween VCC1 and VCC2, the control logic 12 is designed to use bothcapacitors 22 and 26 of the booster 10. In this case, the boostedvoltage VPP from the booster 10 is positioned between VPP1 and VPP2 by aboosting operation using a couple of capacitors. If the power supplyvoltage is leveled between VCC2 and VCC3, the control logic 12 isdesigned to use one of capacitors 22 and 26 of the booster 10. In thiscase, the boosted voltage VPP is positioned between VPP2 and VPP1 by aboosting operation using one capacitor.

[0012]FIG. 2 is a graph VPP(10), which shows a boosted voltage VPPhaving wide variations depending on variations in the power supplyvoltage VCC. It means that an integrated circuit device (which receivesVPP as its power supply) has an unstable operation.

[0013] Therefore, to ensure a stable operation, there exists a need fora voltage boosting circuit that fluctuates very little due to variationsin the power supply voltage.

SUMMARY OF THE INVENTION

[0014] The object of the present invention is to provide a voltageboosting circuit for an integrated circuit which outputs a boostedvoltage with reduced fluctuations as a result of variations in the powersupply voltage.

[0015] According to an aspect of the present invention, the voltageboosting circuit for an integrated circuit includes a booster and avoltage clamp circuit. The booster generates a boosted voltage higherthan the supply voltage in response to a boosting control signal. Thevoltage clamp circuit includes a voltage detector, a pulse generator,and a discharge circuit. The voltage detector generates, in response tothe boosting control signal, a detected voltage signal representing anattribute of the boosted voltage. The pulse generator generates a pulsesignal responsive to the detected voltage signal. And the dischargecircuit discharges the boosted voltage during an activation period ofthe pulse signal. This largely stabilizes the output voltage of thebooster.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be more clearly understood from thedescription of the preferred embodiments as set forth below withreference to the accompanying drawings, wherein:

[0017]FIG. 1 is a circuit diagram showing a voltage boosting circuit inthe prior art;

[0018]FIG. 2 is a graph showing how the boosted voltage of the circuitof FIG. 1 fluctuates if there is a variation in the power supplyvoltage;

[0019]FIG. 3 is a block diagram of a voltage boosting circuit for anintegrated circuit according to an embodiment of the present invention;

[0020]FIG. 4 is a circuit diagram showing the preferred embodiment ofthe voltage boosting circuit of FIG. 3;

[0021]FIG. 5 is a diagram illustrating waveforms of signals and voltagesin the voltage boosting circuit of FIG. 4; and

[0022]FIG. 6 is a graph showing how the boosted voltage of the circuitof FIG. 4 fluctuates if there is a variation in the power supplyvoltage.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0023] Referring now to FIGS. 3-6, a preferred embodiment of the presentinvention is described.

[0024]FIG. 3 is a block diagram showing a voltage boosting circuit of anintegrated circuit device in accordance with the present invention. Avoltage boosting circuit 100 includes booster 110 and voltage clampcircuit 120, which is also known as voltage stabilizer.

[0025] The booster 110 operates in response to a boosting control signalPBST. It generates a boosted voltage VPP, which is higher than theexternally the power supply voltage VCC, which is also called firstsupply voltage. The power supply voltage VCC is typically the oneprovided by the battery in a portable device. The booster 110 operatesby using the first supply voltage VCC, and a second supply voltage lowerthan the VCC. The second supply voltage can be the ground voltage GND.

[0026] The voltage clamp circuit 120 is connected to the VPP generatedfrom the booster 110. The voltage clamp circuit 120 clamps the VPP to adesired level in response to the boosting control signal PBST.

[0027] The voltage clamp circuit 120 is constructed of a voltagedetector 122, a pulse generator 124, and a discharge circuit 126.

[0028] The voltage detector 122 is connected so as to receive theboosted voltage VPP. When the boosted voltage VPP is over a firstpredetermined threshold voltage, the voltage detector 122 generates adetected voltage signal VDET. Signal VDET has a voltage levelrepresenting an attribute of the boosted voltage. In the preferredembodiment, the attribute is a deviation of the instantaneous boostedvoltage VPP from a desired preset voltage VPPd. Accordingly, the signalmay have a magnitude proportional to that deviation.

[0029] The pulse generator 124 generates a pulse signal PL, which ishigh (“activated”) while the voltage level of the VDET is higher thanthe predetermined threshold voltage. Pulse signal PL is input in thedischarge circuit 126.

[0030] The discharge circuit 126 discharges to decrease gradually theVPP while the pulse signal from the pulse generator 124 is activated.

[0031] While the boosted voltage VPP is being gradually decreased, thedetected voltage signal VDET is also being decreased commensurately.When the gradually decreasing boosted voltage VPP attains the desiredlevel, the detected voltage signal VDET becomes such that the pulsesignal PL is no longer generated. Thus, the discharge circuit 126 isdisabled, and it stops discharging of the VPP. Thus the boosted voltageVPP becomes stable at the desired level.

[0032]FIG. 4 shows a preferred embodiment of the voltage boostingcircuit 100 according to the present invention. The components 110, 122,124, 126 are identifiable from FIG. 3.

[0033] The booster 110 is proposed by “Quick Double Bootstrapping Schemefor Word Line of 1.8V Only 16 Mb Flash Memory” (The 6th KoreanConference for Semiconductor, February 1999). It includes inverters 406,414, and 426, PMOS transistors 408, 416, and 428, NMOS transistors 410and 424, depletion-typed MOS transistors 418 and 430, and capacitors 412and 422. The transistors 418 and 430 are designed to withstand highvoltage.

[0034] The voltage detector 122 includes an inverter 432, a PMOStransistor 434, and voltage divider 438. The inverter 432 is suppliedwith the VPP as an operating voltage, and receives the boosting controlsignal PBST.

[0035] The PMOS transistor 434 has a source connected for receiving theboosted voltage VPP and a drain connected to the voltage divider 438. Italso has a gate connected to the inverter 432, for being turned on oroff by the boosting control signal PBST.

[0036] The voltage divider 438 is composed of three NMOS transistors440, 442, and 444, and a resistor 446. The transistors 434, 440, 442,and 444 are designed to be adapted to high voltage, and are connected soas to operate the NMOS transistors as diodes. Their current paths areconnected between the drain of the PMOS transistor 434 and a node A.

[0037] When the boosting control signal PBST goes from a low level to ahigh level, the PMOS transistor 434 is turned on. As a result, theboosted voltage VPP is applied to the voltage detector 122 through thePMOS transistor 434. If the VPP is lower than a voltage corresponding tosum of threshold voltages of the diode-connected NMOS transistors 440,442, and 444, then a current path through them is not turned on. On theother hand, if the VPP is higher than a voltage corresponding to sum ofthreshold voltages of the diode-connected NMOS transistors, the currentpath of the diode-connected NMOS transistors is turned on. In that case,a voltage at node A is a function of the VPP, by operation of theresistor 446. Namely, the VPP is divided by the voltage divider 438, andthereby the divided voltage VDET is provided as a detected value of VPPlevel to the pulse generator 124.

[0038] The pulse generator 124 includes at least one inverter. In theembodiment of FIG. 4, it includes a first inverter and a secondinverter. These are formed as follows.

[0039] The pulse generator 124 includes a resistor 452, two PMOStransistors 454 and 462, and two NMOS transistor 456 and 464. Theresistor 452 and transistors 454 and 456 compose the first invertercircuit, having an output terminal B. A current path of the resistor452, the PMOS transistor 454, and the NMOS transistor 456 is connectedbetween the power supply voltage VCC and the ground voltage GND inseries. Both transistors 454 and 456 are controlled by the detectedvoltage signal VDET.

[0040] The transistors 462 and 464 compose the second inverter circuit,having an output terminal C. A current path of the PMOS transistor 462and the NMOS transistor 464 is connected between the VCC and the GND inseries, and gates of the transistors 462 and 464 is commonly connectedto output terminal B of the first inverter circuit.

[0041] In the first inverter circuit, a logical threshold voltage (ortriggering voltage) of the inverter circuit is accomplished by providingthe VCC through the resistor 452. As a conductivity of a pull-uptransistor (PMOS transistor), which connects the output terminal B withthe power supply voltage VCC becomes low, the logical threshold voltageof the first inverter circuit becomes lower than before. On the otherhand, as a conductivity of a pull-down transistor (NMOS transistor),which connects the output terminal B with the ground voltage GND becomeslow, the logical threshold voltage of the inverter circuit becomeshigher. If the resistor 452 is inserted at the pull-up terminal side,the logical threshold voltage of the inverter circuit becomes low, andthereby reduces fluctuation of the logical threshold voltage affected byvariation of the VCC. More particularly, fluctuation of desired boostedvoltage becomes reduced. Inserting a resistor at the pull-down terminalside can raise the logical threshold voltage of the inverter circuit.

[0042] The second inverter circuit generates a pulse signal PL at nodeC, by inverting the output signal generated at node B from the firstinverter circuit. When the boosted voltage VPP from the booster 110 iscompletely stable, the node A has a voltage level between that of thepower supply voltage VCC and the ground voltage GND. Therefore, theoutput signal from the terminal B has a voltage level also between ahigh-leveled VCC and a low-leveled GND. The second inverter circuitprevents a possible instability of the voltage at node B from affectingthe output.

[0043] The discharge circuit 126 is composed of a NMOS transistor 468having a current path formed between the VPP and the GND, and a gateconnected so as to receive the pulse signal PL generated at node C ofthe pulse generator 124. The transistor 468 is designed to withstand ahigh voltage. The discharge circuit 126 is turned on during anactivation period of the pulse signal PL, and therefore the boostedvoltage VPP is discharged while the discharge circuit 126 is turned on.

[0044]FIG. 5 is a diagram illustrating waveforms of signals and voltagesin the voltage boosting circuit of FIG. 4. Referring to the FIG. 5, theoperation of the voltage boosting circuit will be described below. Whenthe boosting control signal PBST goes from a low level to a high level,the booster 110 generates a boosted voltage VPP voltage, which may havea level Vpeak. Simultaneously, the voltage detector 122 receives theVpeak from the booster 110 in response to the PBST having a low-to-hightransition.

[0045] Level Vpeak may be higher than a desired boosted voltage VPPd. Ifthat happens, then by proper design the inputted voltage of the voltagedetector 122 is higher than the sum of the threshold voltages of NMOStransistors 440, 442, and 444 in the voltage divider 438. Then thevoltage detector 122 generates a detected voltage signal VDET having avoltage level determined by the input voltage VPP. Then, the pulsesignal PL goes from a low level to a high level when the detectedvoltage signal VDET is over a logical threshold voltage VLT1 of thefirst inverter circuit 452, 454, and 456 corresponding to thelow-to-high transition. The NMOS transistor 468 of the discharge circuit126 is turned on by the pulse signal having a low-to-high transition,and thereby the boosted voltage VPP from the booster 110 becomesgradually low.

[0046] When the VPP from the booster 110 is decreased down to thedesired boosted voltage level VPPd, it is prevented from being reducedfurther. This takes place as follows.

[0047] As the VPP is approaching the VPPd level, the detected voltagesignal VDET at the node A is also being gradually and commensuratelydecreased. Then, the signal VDET crosses a logical threshold voltageVLT2 of the first inverter circuit 452, 454, and 456 in the pulsegenerator 124 corresponding to a high-to-low transition. Thus, thevoltage at node B starts to increase gradually from the ground voltageGND. After a short while, the pulse signal PL from the node C goes froma high level of the power supply voltage VCC to a low level of theground voltage GND. This causes the discharge circuit 126 to stopdischarging. Thus, the VPP from the booster 110 is maintained to thedesired boosting voltage VPPd.

[0048] As an additional advantage, the voltage clamp circuit 120 helpsthe VPP reach equilibrium fast. The maximum voltage Vpeak or an initialvoltage of the booster 110 can be reduced to be near the VPPd in lessthan about 21 nsec.

[0049]FIG. 6 is a graph comparing the performance of the invention [lineVPP(100)] with that of the prior art [line VP(10), repeated from FIG.2]. It will be observed that line VP(100) is a lot smoother than lineVP(10), as a result of the voltage clamp circuit 120 of the presentinvention. Indeed, VPP(100) varies from 5.31V to 5.67V, while VPP(10)varies between 4.80V and 5.67V.

[0050] For FIG. 6, the power supply voltage VCC assumes the values of2.5V, 3V, 3.3V, 3.5V, 3.8V, and 4V. The one capacitor used in thebooster 100 of the present invention occupies 6,498 mm2 of the voltageboosting circuit, which is exactly the same topological size as thecapacitors 22 and 26 used in the prior art booster 10 of FIG. 1 (2*3,249mm2).

[0051] According to the present invention, detecting the boosted voltagefrom the booster and discharging the boosted voltage in accordance withthe detected voltage can be minimize the fluctuation of the boostedvoltage affected by variation of the power supply voltage.

What is claimed is:
 1. A voltage boosting circuit for an integrated circuit, comprising: a booster for generating a boosted voltage higher than a first supply voltage by using a first supply voltage and a second supply voltage lower than the first supply voltage, in response to a boosting control signal; a voltage detector for generating a detected voltage signal representing an attribute of the boosted voltage, in response to the boosting control signal; a pulse generator for generating a pulse signal responsive to a voltage level of the detected voltage signal; and a discharge circuit for providing a current path so as to discharge the boosted voltage during an activation period of the pulse signal.
 2. The circuit of claim 1, wherein the voltage detector senses a level of the boosted voltage.
 3. The circuit of claim 1, wherein the attribute is a deviation of the instantaneous boosted voltage from a desired preset voltage.
 4. The circuit of claim 1, wherein the voltage detector includes: an inverter for inverting the boosting control signal; a switch transistor having a first terminal connected to receive the boosted voltage, a gate terminal connected to receive an output signal from the inverter and a third terminal; and a voltage divider connected between the third terminal of the switch transistor and the second supply voltage.
 5. The circuit of claim 4, wherein the inverter is operated from the boosted voltage.
 6. The circuit of claim 4, wherein the voltage divider includes: a plurality of diode-connected transistors connected in series between the boosted voltage and an output terminal of the voltage divider; and a resistor connected between the output terminal of the voltage divider and the second supply voltage.
 7. The circuit of claim 6, wherein the diode-connected transistors are formed of enhancement-type MOS transistors.
 8. The circuit of claim 1, wherein the pulse generator includes an inverter connected between the voltage detector and the discharge circuit.
 9. The circuit of claim 1, wherein the pulse generator includes first and second inverters connected successively between the voltage detector and the discharge circuit in series, and the first inverter receives the first supply voltage through a resistor.
 10. The circuit of claim 1, wherein the discharge circuit is formed of a NMOS transistor. 